1. Field of the Invention
The present invention relates to a clock change circuit receiving two clock signals, and selecting one of the clock signals for use.
The present invention relates, in particular, to a clock change circuit receiving two clock signals, and selecting one of the two clock signals for use, where the duty ratios of the two clock signals are equal, and the phase of one of the two clock signals selected after a clock change is delayed by a phase difference not less than 0.degree. and less than a duration in which each of the clock signals is at an active level in a cycle, from the phase of the other of the two clock signals selected before the clock change.
The present invention is applicable, in particular, to a clock change circuit provided in a master apparatus (network termination apparatus) to which a plurality of terminals are bus-connected according to the CCITT recommendation I.430. In such a clock change circuit, an operation of changing a receiving clock is performed from a clock signal extracted (regenerated) from data received from a terminal nearest the master apparatus to a fixed clock signal generated in the master apparatus. Data transmitted from the terminals are received in synchronization with the receiving clock.
2. Description of the Related Art
In the above construction of the CCITT recommendation I.430, one of the terminals may continuously supply data to the master apparatus when the receiving clock signal is changed from one to the other. The data is required to be received continuously by the master apparatus without a trouble when the receiving clock signal is changed from one to the other.
The CCITT recommendation I.430 provides recommendations for constructing a system comprising a network termination apparatus to which one or plurality of terminals are connected through a two-way transmission line (bus), and in the system the network termination apparatus can simultaneously receive signals output from two terminals, where the signals output from two terminals are synthesized on the same bus to generate a synthesized signal, and the network termination apparatus receives the synthesized signal and recognizes the respective signals contained in the synthesized signal. In the system according to the CCITT recommendation I.430, although generally more than two terminals can be connected to the two-way transmission line (bus) which is connected to the network termination apparatus, at most two terminals among the more than two terminals simultaneously output signals to the network termination apparatus.
In the system according to the CCITT recommendation I.430, the receiving clock of the network termination apparatus is obtained from a phase-locked loop (PLL) circuit which extracts a clock signal synchronized with the rise time of a frame synchronization bit contained in a frame received from a terminal nearest the network termination apparatus so that the receiving clock synchronizes with data received from the terminal nearest the network termination apparatus, of the two terminals simultaneously transmitting signals to the network termination apparatus. Further, in the network termination apparatus according to the CCITT recommendation I.430, when the network termination apparatus detects that a delay in a phase of a clock signal extracted from a signal received from the nearest terminal is less than a predetermined value (that is, a distance from the network termination apparatus to the nearest terminal is very small), the receiving clock is changed from the above clock signal synchronized with the signal received from the nearest terminal, to a fixed clock generated in the network termination apparatus. Inversely, when the network termination apparatus detects that a delay in a phase of a clock signal extracted from a signal received from the nearest terminal nearest terminal is not less than the predetermined value (that is, a distance from the network termination apparatus to the nearest terminal is not very small), the receiving clock is changed from a fixed clock generated in the network termination apparatus, to the above clock signal synchronized with the signal received from the nearest terminal.
Therefore, in the first case wherein one of two terminals simultaneously transmitting signals to the network termination apparatus, stops the transmission of the signal, and the terminal which stops the transmission is located nearest the network termination apparatus; or in the case wherein a first terminal of first and second terminals simultaneously transmitting signals to the network termination apparatus stops the transmission of the signal, then a third terminal other than the above first and second terminals begins transmission of a signal, and the first or third terminal is located nearest the network termination apparatus, the nearest terminal is changed, and the above change of the receiving clock between the fixed clock generated in the network termination apparatus, and the above clock signal synchronized with the signal received from the nearest terminal, may be performed dependent upon the distance from the network termination apparatus to the nearest terminal.
The CCITT recommendation I.430 recommends three types of configurations as indicated in FIGS. 1, 2, and 3. In FIGS. 1, 2, and 3, DSU denotes a digital service unit (network termination apparatus), TE denotes a terminal, and TR denotes a termination resistance. The configuration of FIG. 1 is called a short distance passive bus connection. In the short distance passive bus connection configuration, the distance d2 from the digital service unit DSU to the termination resistance TR is 100 to 200 meters, the terminal TE is allowed to be connected to an arbitrary position between the digital service unit DSU to the termination resistance TR. The configuration of FIG. 2 is called an extended passive bus connection. In the extended passive bus connection configuration, a line extension, i.e., a distance d4 from the digital service unit DSU to the farthest terminal TE is at least 500 meters, the distance d3 between two terminals TE simultaneously transmitting signals to the digital service unit DSU is limited within a range of 25 to 50 meters. The configuration of FIG. 3 is called a point-to-point connection. In the point-to-point connection configuration, only one terminal TE transmits a signal to the digital service unit DSU. The digital service unit DSU is connected to an end of the transmission line, and the terminal TE is connected to the other end of the transmission line. The distance d1 from the digital service unit DSU to the terminal TE is, for example, 1 kilometers.
Generally, when more than two terminals are connected to the two-way transmission line (bus) which is connected to the digital service unit DSU (network termination apparatus), the configuration may be changed from one to another of the three configurations of FIGS. 1, 2, and 3, according to change of the two terminals TE which transmit signals to the digital service unit DSU (network termination apparatus).
In the case considered here, one of the two terminals transmitting signals to the digital service unit DSU is changed to another terminal while the other of the two terminals continuously transmitting signals carrying information which must be transmitted to the digital service unit DSU without intermission. In this case, the receiving clock must be changed without trouble when the change is required according to the change of the terminal which transmits a signal, so that the above information which must be transmitted to the digital service unit DSU without intermission, can be received by the digital service unit DSU without trouble.
According to the above configurations of FIGS. 1, 2, and 3, a relative delay between the signals transmitted from the two terminals TE, is estimated to be at most 2 microseconds when the period of one bit is 5.2 microseconds, that is, at most about 40% of a period. As explained later, a condition is assumed that in the change of the receiving clock between the fixed clock generated in the network termination apparatus, and the above clock signal synchronized with the signal received from the nearest terminal, the phase of the fixed clock signal is preset so that the phase of the clock signal before the change is in advance to the phase of the clock signal after the change, when duty ratios of the above clock signals before and after the change are 50%. Such a setting of the phase of the fixed clock signal is possible by appropriately setting a delay in the fixed clock signal with regard to a transmitting clock signal in the digital service unit DSU.
Thus, the requirement for the clock change circuit used in the digital service unit DSU of the CCITT recommendation I.430, is to assure that the information which must be transmitted to the digital service unit DSU without intermission, can be received by the digital service unit DSU when the receiving clock is changed to one to the other of two clock signals when the duty ratios of the two clock signals are 50%, and the phase of one of the two clock signals selected after a clock change is delayed from the phase of the other of the two clock signals selected before the clock change by a phase difference pd in a range 0.degree..ltoreq.pd&lt;180.degree..
In addition, the clock change circuit satisfying the above requirement can be used in applications other than the digital service unit DSU according to the CCITT recommendation I.430.
Further, generally, the clock change circuit satisfies requirements that a receiving clock can be changed from one to the other of two clock signals without trouble when the duty ratios of the two clocks are equal, and the phase of one of the two clock signals selected after a clock change is delayed by a phase difference not less than 0.degree. and less than a duration in which each of the clock signals is at an active level in a cycle, from the phase of the other of the two clock signals selected before the clock change.
FIG. 4 is a diagram illustrating a conventional clock change circuit. The construction of FIG. 4 is comprised of a 2-1 selector which simultaneously receives two clock signals A and B at two input terminals thereof, and selects one of the received signals according to a change control signal CHNG received at a control input terminal SEL thereof, to output the selected signal.
FIGS. 5A to 5D are timing diagrams of an operation of the construction of FIG. 4 when the phase of the clock signal B which is selected after the change is delayed by a phase difference in a range not less than 0.degree. and less than 180.degree., from the phase of the clock signal A which is selected before the clock change. As indicated in FIGS. 5A to 5D, a spike as shown may appear in the output of the construction of FIG. 4 when the clock signal is changed. When such a spike appears in the receiving clock a problem such as reading the same data twice, may occur.
FIG. 6 is a diagram illustrating another conventional clock change circuit, which is provided for avoiding the generation of a spike in the output of the construction of FIG. 4.
In the construction of FIG. 6, reference numeral 111 denotes a D-type flip-flop circuit, 112 and 113 each denote a 2-1 selector. Both the clock signals A and B, which are respectively selected before and after the clock change, are applied to two input terminals of each of the two 2-1 selectors 112 and 113. A change signal CHNG, which is supplied to the construction of FIG. 6 from outside to instruct the clock change, is applied to the data input terminal D of the D-type flip-flop circuit 111. The output of the 2-1 selector 113 is applied to the clock input terminal (edge-triggered input terminal) CK of the D-type flip-flop circuit 111, and the Q output of the D-type flip-flop circuit 111 is applied to control input terminals of the two 2-1 selectors 112 and 113 as a select control input signal.
FIGS. 7A to 7E are timing diagrams of an operation of the construction of FIG. 6 when the phase of the clock signal B which is selected after the change is delayed by a phase difference in a range not less than 0.degree. and less than 180.degree., from the phase of the clock signal A which is selected before the clock change. As indicated in FIGS. 7A to 7E, no spike appears in the output of the construction of FIG. 6.
However, in the above construction of FIG. 6, the hardware size is increased due to the use of two 2-1 selectors.